Instruction Set Architecture

ThruVM implements a RISC-V virtual machine that executes smart contract bytecode on the Thru blockchain. The VM is fully compliant with the RISC-V specification and supports multiple standard extensions for comprehensive computational capabilities.

Execution on ThruVM is single-threaded and is entirely deterministic. There is no atomic access to data outside virtual machine execution, which implies sequential consistency for all memory operations.

RISC-V Specification Compliance

ThruVM is fully compliant with the RISC-V Instruction Set Manual, Version 20250508. The implementation adheres to all architectural requirements and behavioral specifications defined in this version.

Note

All instructions are aligned to 16-bits (IALIGN=16) as per the RISC-V specification. Unaligned data access is not supported and will result in an exception. See Programmer and Implementer Considerations for more details.

Supported Extensions

ThruVM supports the following RISC-V instruction set extensions:

Extension ID	Name	Version	Purpose
RV64I	Base Integer Instruction Set	2.1	64-bit base integer instructions including arithmetic, logical, memory, and control flow operations
M	Standard Extension for Integer Multiplication and Division	2.0	Hardware multiplication, division, and remainder operations for both 32-bit and 64-bit integers
C	Standard Extension for Compressed Instructions	2.0	16-bit compressed instruction encodings to reduce code size and improve instruction fetch efficiency
B	Standard Extension for Bit Manipulation	1.0.0	Bit manipulation instructions including count, rotate, permute, and logic operations
Zknh	NIST Suite: Hash Function Instructions	1.0.1	Cryptographic hash function acceleration instructions for SHA-256 and SHA-512

Instruction Set Architecture Details

The following sections provide a brief description of the base ISA and supported extensions.

Base ISA (RV64I)

The RV64I base instruction set provides:

• 64-bit integer registers: 32 general-purpose registers (x0-x31) with x0 hardwired to zero
• Load/Store architecture: Memory access only through explicit load and store instructions
• Arithmetic operations: Addition, subtraction, logical operations (AND, OR, XOR)
• Shift operations: Logical and arithmetic left/right shifts
• Comparison operations: Set-less-than for signed and unsigned comparisons
• Branch instructions: Conditional branches based on register comparisons
• Jump instructions: Unconditional jumps with optional link register updates
• System instructions: Environment calls and control/status register access

Multiplication and Division (M Extension)

The M extension adds support for:

• Integer multiplication: MUL, MULH, MULHSU, MULHU
• Integer division: DIV, DIVU, REM, REMU
• 32-bit variants: MULW, DIVW, DIVUW, REMW, REMUW for RV64

Compressed Instructions (C Extension)

The C extension provides 16-bit instruction encodings for:

• Common operations: Register-register operations, immediate operations
• Memory access: Compressed load/store instructions
• Control flow: Compressed branch and jump instructions
• Stack operations: Stack pointer manipulation instructions

Tip

For optimal resource efficiency, use the compressed instructions to reduce compute unit consumption.

Bit Manipulation (B Extension)

The B extension includes instructions for:

• Bit counting: Count leading/trailing zeros (CLZ, CTZ)
• Bit manipulation: Single-bit operations, bit field operations
• Rotation: Left and right rotations (ROL, ROR)
• Permutation: Byte and nibble permutation operations
• Carry-less multiplication: CLMUL, CLMULH, CLMULR

Cryptographic Hash Functions (Zknh Extension)

The Zknh extension provides acceleration for:

• SHA-256: SHA256SIG0, SHA256SIG1, SHA256SUM0, SHA256SUM1
• SHA-512: SHA512SIG0, SHA512SIG1, SHA512SUM0, SHA512SUM1

Programmer and Implementer Considerations

Illegal Instructions

Using instructions that are currently unimplemented will cause the VM to exit with an illegal instruction exception (SIGILL), resulting in transaction revert.

If an instruction becomes implemented in future versions, programs using those instruction encodings will automatically adopt the new behavior. To explicitly indicate illegal instructions, use encodings with all bits set to 0 or all bits set to 1.

Memory Alignment

ThruVM enforces strict alignment requirements:

• Instructions: Must be aligned to 16-bit boundaries
• Data access: Unaligned memory access is not supported and will trigger an exception

System Calls

For details on the syscall calling convention and available system calls, refer to the Syscalls documentation.

Register Conventions

ThruVM follows standard RISC-V register conventions:

Register	ABI Name	Purpose
x0	zero	Hardwired to zero
x1	ra	Return address
x2	sp	Stack pointer
x3	gp	Global pointer
x4	tp	Thread pointer
x5-x7	t0-t2	Temporary registers
x8	fp/s0	Frame pointer/saved register
x9	s1	Saved register
x10-x17	a0-a7	Function arguments/return values
x18-x27	s2-s11	Saved registers
x28-x31	t3-t6	Temporary registers